Patent Literature 1 discloses a configuration (see FIG. 19) of a flip-flop provided in each stage of a shift register in a driver circuit, and a drive method (FIG. 20) of the flip-flop. As illustrated in FIG. 20, in this flip-flop, a first initialization signal (AON signal), a second initialization signal (AONB signal), and first and second clock signals CK1 and CK2 are set as follows. In a period to in which respective stages of the shift register are active (hereinafter, this is referred to as an all-ON operation, the AON signal is set High (active), the AONB signal is set Low (active) and CK1 and CK2 are set High. In a period tb after the completion of the all-ON operation, the AON signal is set Low (inactive), the AONB signal is set High (inactive) and CK1 and CK2 are set High. Further, in a period tc following the period tb, the AON signal is set Low (inactive), the AONB signal is set High (inactive) and CK1 and CK2 are set Low and an operation shifts to a regular operation.